HT82K74EE datasheet(25/56 Pages) HOLTEK

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HT82K74E/HT82K74EE

Rev. 1.00

December 15, 2009

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and its corresponding timer in-

terrupt enable bit, ETI, must first be set. An actual

Timer/Event Counter interrupt will take place when the

Timer/Event Counter request flag, TF, is set, a situation

that will occur when the Timer/Event Counter overflows.

When the interrupt is enabled, the stack is not full and a

Timer/Event Counter overflow occurs, a subroutine call

to the timer interrupt vector at location 08H, will take

place. When the interrupt is serviced, the timer interrupt

request flag, TF, will be automatically reset and the EMI

bit will be automatically cleared to disable other inter-

rupts.

Programming Considerations

By disabling the interrupt enable bit, the requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the interrupt control register until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode.

Only the Program Counter is pushed onto the stack. If

the contents of the accumulator or status register are al-

tered by the interrupt service program, which may cor-

rupt the desired control sequence, then the contents

should be saved in advance.

I N T C R e g i s t e r

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

N o i m p l e m e n t e d , r e a d a s " 0 "

b 7

b 0

E T I

E M I

T i m e r / E v e n t C o u n t e r I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T F

N o i m p l e m e n t e d , r e a d a s " 0 "

Interrupt Control Register

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