MPC8535E datasheet(85/126 Pages) FREESCALE

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I2C

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.17.2

I2C AC Electrical Specifications

Table 64 provides the AC timing parameters for the I

2C interfaces.

Pulse width of spikes which must be suppressed by the input

filter

tI2KHKL

050

Input current each I/O pin (input voltage is between 0.1

OVDD and 0.9 × OVDD(max)

–10

μA3

Capacitance for each I/O pin

—10

—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. See the

MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used.

3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.

Table 64. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 63).

Parameter

Symbol 1

Min

Max

Unit

Notes

SCL clock frequency

fI2C

400

kHz

—

Low period of the SCL clock

tI2CL

1.3

—

μs—

High period of the SCL clock

tI2CH

0.6

—

μs—

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs—

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

tI2SXKL

0.6

—

μs—

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

μs2

Data output delay time

tI2OVKL

—0.9

—

Set-up time for STOP condition

tI2PVKH

0.6

—

μs—

Rise time of both SDA and SCL signals

tI2CR

—

300

Fall time of both SDA and SCL signals

tI2CF

—

300

Table 63. I2C DC Electrical Characteristics (continued)

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

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