MPC8536AVTATH datasheet(32/128 Pages) FREESCALE

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MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

DDR2 and DDR3 SDRAM

Freescale Semiconductor

2.6

DDR2 and DDR3 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8536E. Note that

DDR2 SDRAM is GVDD(type) = 1.8 V and DDR3 SDRAM is GVDD(type) = 1.5 V.

2.6.1

DDR2 and DDR3 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8536E when

interfacing to DDR2 SDRAM.

Table 13 provides the recommended operating conditions for the DDR SDRAM Controller of the MPC8536E when interfacing

to DDR3 SDRAM.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.7

1.9

I/O reference voltage

MVREF

0.49

× GVDD

0.51

× GVDD

I/O termination voltage

VTT

MVREF –0.04

MVREF + 0.04

Input high voltage

VIH

MVREF+0.125

GVDD +0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.125

—

Output leakage current

IOZ

–50

μA4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ GVDD.

Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.425

1.575

I/O reference voltage

MVREFn

0.49

× GVDD

0.51

× GVDD

Input high voltage

VIH

MVREFn + 0.100

GVDD

V—

Input low voltage

VIL

GND

MVREFn – 0.100

—

Output leakage current

IOZ

–50

μA3

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.

Peak-to-peak noise on MVREFn may not exceed ±1% of the DC value.

3. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ GVDD.

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