MPC8548E datasheet(14/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

Power Characteristics

NOTE

In order to guarantee MCKE low during power-up, the above sequencing for

GVDD is required. If there is no concern about any of the DDR signals being

in an indeterminate state during power-up, then the sequencing for GVDD is

not required.

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the

VDD core supply, the I/Os associated with that I/O supply may drive a logic

one or zero during power-up, and extra current may be drawn by the device.

Power Characteristics

The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this

family of PowerQUICC III devices is shown in Table 4.

Table 4. MPC8548E Power Dissipation

CCB Frequency1

Core Frequency

SLEEP2

Typical-653

Typical-1054

Maximum5

Unit

400

800

2.7

4.6

7.5

8.1

1000

2.7

5.0

7.9

8.5

1200

2.7

5.4

8.3

8.9

500

1500

11.5

13.6

16.5

18.6

533

1333

6.2

7.9

10.8

12.8

Notes:

1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.

2. SLEEP is based on VDD = 1.1 V, Tj = 65°C.

3. Typical-65 is based on VDD = 1.1 V, Tj = 65°C, running Dhrystone.

4. Typical-105 is based on VDD = 1.1 V, Tj = 105°C, running Dhrystone.

5. Maximum is based on VDD = 1.1 V, Tj = 105°C, running a smoke test.

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