| 전자부품 데이터시트 검색엔진 |
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ASDL-7021 데이터시트(PDF) 11 Page - Lite-On Technology Corporation |
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ASDL-7021 데이터시트(HTML) 11 Page - Lite-On Technology Corporation |
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11 / 23 page ![]() Clock Standards Standard values of the system clock input Frequency: 48MHz ± 100ppm Input Duty: Must be within 50% ± 5%. Power-up Procedures V t VDDK(=1.8V) VDDC,VIO(=1.8 to 3.3V) V t VDDK(=1.8V) VDDC,VIO(=1.8 to 3.3V) V V Recommended Power-Up Procedure Allowable Limit of Power-Up Procedure Turn on the core power supply VDDK before you turn on the VDDC and VIO power supply and shut it down later If you want to turn on the core power supply VDDK after you turn on VDDC and VIO power supply, you must keep V = VIO-VDDK < 0.5V during the time before VDDK becomes stable |
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