ST7558 datasheet(21/56 Pages) SITRONIX

21 / 56 page

ST7558

Ver 2.3

21/56

2005/10/05

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 10. It incorporates 4-bit Page

Address register changed by only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and

display data D0 is only valid.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in

figure10. The display data RAM column address is specified by the Column Address Set command. The specified column

address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed

continuously.

segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction.

SEG Output

SEG0

SEG101

“0”

seg0

Segment Address

seg101

“1”

seg101

Segment Address

seg0

Com Output

COM Output

Com0

Com64

“0”

com0

Common Address

com64

“1”

com64

Common Address

com0

ADDRESSING

Data is downloaded in bytes into the RAM matrix of ST7558 as indicated in Figs.10, 11,12. The display RAM has a matrix

of 65 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 8

(1000). Addresses outside these ranges are not allowed.

In vertical addressing mode (V=1) the Y address increments after each byte (see Fig.11). After the last Y address (Y = 8) Y

wraps around to 0 and X increments to address the next column.

In horizontal addressing mode (V=0) the X address increments after each byte (see Fig.12). After the last X address

(X = 101) X wraps around to 0 and Y increments to address the next row.

After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)

Data structure

LSB

MSB

101

X-address

1 bit

Page 8

1 bit

Page 9

1 bit

ICOM

Fig.10 RAM format, addressing

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