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ST7632 데이터시트(PDF) 23 Page - Sitronix Technology Co., Ltd. |
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ST7632 데이터시트(HTML) 23 Page - Sitronix Technology Co., Ltd. |
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23 / 96 page ![]() ST7632 Ver 1.7 23/96 2006/08/15 7-3 DISPLAY DATA RAM (DDRAM) 7.3.1 DDRAM It is 396 X 132 X 4 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of RGB, data transfer related restrictions are reduced, realizing the display flexing. The RAM on ST7632 is separated to a block per 4 lines to allow the display system to process data on the block basis. MPU ’s read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration. Memory Map (When using the 8 gray-scale. 8-bit mode) RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column P11:0 0 1 131 P11:1 131 130 0 Color R G B R G B R G B LCD read direction Data Page Block P10:0 P10:1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 131 1 130 2 129 0 3 128 4 127 5 126 6 125 1 7 124 8 123 2 9 122 124 7 125 6 126 5 31 127 4 128 3 129 2 130 1 32 131 0 SEGout 0 1 2 3 4 5 393 392 395 |
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