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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST8008 데이터시트(PDF) 17 Page - Sitronix Technology Co., Ltd. |
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ST8008 데이터시트(HTML) 17 Page - Sitronix Technology Co., Ltd. |
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17 / 21 page  ST8008 V0.3 17/21 2004/04/05 AC Characteristics (VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL CONDITIONS MIN TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF ≤ 11ns 125 ns 1 Shift clock "H" pulse width tWCKH 51 ns Shift clock "L" pulse width tWCKL 51 ns Data setup time tDS 30 ns Data hold time tDH 40 ns Latch pulse "H" pulse width tWLPH 51 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 51 ns Latch pulse rise to shift clock rise time tLS 51 ns Latch pulse fall to shift clock fall time tLH 51 ns Latch pulse fall to shift clock rise time tLSW 50 ns Enable setup time tS 36 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 78 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 µs Output delay time (3) t PD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85 °C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF ≤ 10ns 66 ns 1 Shift clock "H" pulse width tWCKH 23 ns Shift clock "L” pulse width tWCKL 23 ns Data setup time tDS 15 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 50 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Latch pulse fall to shift clock rise time tLSW 50 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 41 ns Output delay time (2) tPD1, tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES:1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. |
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