ENC424J600 datasheet(49/168 Pages) MICROCHIP

49 / 168 page

 2010 Microchip Technology Inc.

DS39935C-page 47

ENC424J600/624J600

4.6.2

UNBANKED SFR OPERATIONS

The N-byte unbanked SFR instructions are WCRU,

RCRU

, BFSU and BFCU. These instructions use an

opcode with a one-byte address argument and do not

depend on the use of BxSEL instructions for SFR bank

selection.

Figure 4-6 shows the timing relationships for these

operations. Like all other opcodes, data is presented on

the SI pin, MSb first. For this class of instructions, the

first byte of data is a specific opcode; the second byte

is the 8-bit absolute address of the target SFR. If the

instruction is a write or bit set/clear opcode, the next

bytes are the data or bit mask to be written. For read

instructions, the next bytes are don’t cares.

For write and bit set/clear instructions, the SO pin is

actively driven with indeterminate ‘1’s or ‘0’s while the

CS pin is driven low. For read instructions, random data

is clocked out on SO during SCK clocks, 1 through 16.

Starting with the 17th clock, data is clocked out

byte-wise on SO, MSb first. As with three-byte

instructions, the lower byte of a data word is presented

first, followed by the upper byte.

As long as the CS pin is held low, the instruction

continues to execute, automatically incrementing to the

next register address in the SFR space and writing data

from SI to, or outputting data on SO from, subsequent

registers. When the end of a bank is reached, the

address continues to the top of the next bank.

Addresses continue to increment through the banks

into the unbanked SFR area (addresses 80h through

9Fh), then wrap around to the start of Bank 0 (00h). The

SFR bank value used by the BxSEL and RBSEL

opcodes is not affected by the execution of unbanked

SFR instructions.

There are four unbanked SFR opcodes, summarized in

Table 4-5. Except for addressing, the unbanked SFR

instructions are analogous to the banked SFR instruc-

tions. However, there are certain differences in their

behavior with certain pointer registers, as noted below.

FIGURE 4-6:

N-BYTE SPI OPCODE (UNBANKED SFR OPERATIONS)

SCK

Hi-Z

a5 a4 a3 a2 a1 a0

d7 d6 d5 d4 d3 d2 d1

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Opcode

Unbanked SFR Address

Write 1st Byte

25 26 27

D7 D6 D5

Additional

c1 0

SCK

Hi-Z

d7 d6 d5 d4 d3 d2 d1 d0

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Opcode

Unbanked SFR Address

Read 1st Byte

25 26 27

D7 D6 D5

Additional

c1 0

a5 a4 a3 a2 a1 a0

Write Operation

Read Operation

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