PCA9536_5

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 05 — 25 January 2010

7 of 22

NXP Semiconductors

PCA9536

6.4 Device address

6.5 Bus transactions

Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7

and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in

Figure 9 and Figure 10. These devices do not implement an auto-increment function, so

once a command byte has been sent, the register which was addressed will continue to

be accessed by reads until a new command byte has been sent.

Remark: At power-on reset, all registers return to default values.

Fig 5.

Simplified schematic of IO0 to IO3

IO0 to IO3

output port

register data

configuration

register

DQ

CK

Q

data from

shift register

write configuration

pulse

output port

register

DQ

CK

write pulse

polarity inversion

register

DQ

CK

data from

shift register

write polarity

pulse

input port

register

DQ

CK

read pulse

input port

register data

polarity inversion

register data

002aab852

FF

data from

shift register

FF

FF

FF

Q1

100 k

Ω

Q2

Fig 6.

PCA9536 device address

R/W

002aab853

1

0

0

0

0

0

1

fixed

slave address