PCF2129AT datasheet(45/68 Pages) NXP

45 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

45 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

9.1 SPI-bus interface

Data transfer to and from the device is made via a 3 line SPI-bus (see Table 48). The data

lines for input and output are split. The data input and output line can be connected

together to facilitate a bidirectional data bus (see Figure 27). The SPI-bus is initialized

whenever the chip enable line pin CE is inactive.

[1]

The chip enable must not be wired permanently LOW.

9.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes will be either data to be written

or data to be read (see Figure 28).

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the

following bytes will be read or write information.

Fig 27. SDI, SDO configurations

Table 48.

Serial interface

Symbol

Function

Description

SDA/CE

chip enable input;

active LOW

[1]

when HIGH, the interface is reset;

input may be higher than VDD

SCL

serial clock input

when CE is HIGH, input may float;

input may be higher than VDD

SDI

serial data input

when CE is HIGH, input may float;

input may be higher than VDD;

input data is sampled on the rising edge of SCL

SDO

serial data output

push-pull output;

drives from VSS to VBBS;

output data is changed on the falling edge of SCL

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SDI

two wire mode

SDO

SDI

single wire mode

SDO

Fig 28. Data transfer overview

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data bus

COMMAND

DATA

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