AD9992BBCZ datasheet(27/92 Pages) AD

27 / 92 page

AD9992

Rev. C | Page 27 of 92

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 3

REGION 1: USE V-SEQUENCE 2

REGION 2: USE V-SEQUENCE 1

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 3: USE V-SEQUENCE 0

REGION 4: USE V-SEQUENCE 2

FIELD 0

FIELD1

FIELD2

REGION 2: USE V-SEQUENCE 3

FIELD0

FIELD1

FIELD2

FIELD3

FIELD4

FIELD5

FIELD1

FIELD4

FIELD2

VPAT0

VPAT1

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

CREATE THE VERTICAL PATTERN GROUPS,

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,

GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.

V-SEQUENCE 0

(VPAT0, 1 REP)

V-SEQUENCE 1

(VPAT1, 2 REP)

V-SEQUENCE 2

(VPAT1, N REP)

BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS

AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH

(MAXIMUM OF NINE REGIONS IN EACH FIELD).

USE THE MODE REGISTERS TO CONTROL WHICH FIELDS

ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN

FIELDS CAN BE COMBINED IN ANY ORDER).

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

XV1

XV2

XV23

XV24

XV3

Figure 33. Summary of Vertical Timing Generation

AD9992BBCZ 데이터시트(PDF) 27 Page - Analog Devices

AD9992BBCZ 데이터시트(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL