ADRF6602ACPZ-R7 datasheet(5/24 Pages) AD

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ADRF6602

Rev. 0 | Page 5 of 24

LOGIC INPUT AND POWER SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized

using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

CLK, DATA, LE

Input High Voltage, VINH

1.4

3.3

Input Low Voltage, VINL

0.7

Input Current, IINH/IINL

0.1

μA

Input Capacitance, CIN

POWER SUPPLIES

VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range

4.75

5.25

Supply Current

PLL only

External LO mode (internal PLL disabled,

IP3SET pin = 3.3 V)

165

Internal LO mode (internal PLL enabled,

IP3SET pin = 3.3 V)

262

Power-down mode

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 4.

Parameter

Limit

Unit

Description

ns min

LE setup time

ns min

DATA to CLK setup time

ns min

DATA to CLK hold time

ns min

CLK high duration

ns min

CLK low duration

ns min

CLK to LE setup time

ns min

LE pulse width

Timing Diagram

CLK

DATA

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

Figure 2. Timing Diagram

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