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AS1539/AS1541

Data Sheet - D e t a i l e d D e s c r i p t i o n

8 Detailed Description

The AS1539/AS1541 successive approximation register (SAR) A/D converter architecture is based on capacitive

redistribution which inherently includes a sample-and- hold function.

The AS1539/AS1541 core is controlled by an internally generated free-running clock. When the device is not perform-

ing conversions or being addressed, the A/D converter-core and internal clock are powered off.

Figure 22. Simplified I/O Diagram

Analog Input

When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal capacitor

array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period,

the source must charge the internal sampling capacitor (typically 15pF). After the capacitor has been fully charged,

there is no further input current. The amount of charge transfer from the analog source to the converter is a function of

conversion rate.

Figure 23. Reference circuit

AS1539/

AS1541

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

GND

A0

SCL

SDA

A1

COM

Microcontroller

0.1 to

10µF

2k

Ω

+2.7 to

+5.25V

+

0.1 to

10µF

+

1µF

AS1539

CH0:CH7

SDA

0.1 to

10µF

2k

Ω

+2.7 to

+5.25V

+

1µF

10

Ω

1nF

-

+

VIN