CHA2095a

36-40GHz Low Noise Amplifier

Ref. : DSCHA20958147

6/7

Specifications subject to change without notice

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Typical Bias Tuning for Low Noise Operation

The circuit schematic is given below :

IN

OUT

Vd

Vg 1,2

Vg 3,4

Vd

100

100

50

50

For low noise operation, a separate access to the gate voltages of the two first stages ( Vg1,2 ), and

of the two last stage ( Vg3,4 ) is provided. Nominal bias is obtained for a typical current of 60 mA for

the output stages and 30 mA for the two first stages ( 90 mA for the amplifier ).

The first step to bias the amplifier is to tune Vg1,2 = -1V, and Vg3,4 to drive 60 mA for the full

amplifier. Then Vg1,2 is increased to obtain 90 mA of current through the amplifier. A fine tuning of

the noise figure may be obtained by modifying the Vg1,2 bias voltage, but keeping the previous value

for Vg3,4.

It is possible to reduce the total DC current by biasing Vg3,4 to a more negative value. The

consequences will be a reduction of gain and of the output power capabilities of the amplifier.

Vd could be adjust in such a way that the Vds ( Drain to Source voltage of the internal transistor ) is

kept below 3.5V, knowing that all the transistor have the same size, and with the given resistors.

Ordering Information

Chip form

:

CHA2095a99F/00

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otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

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