AS3910 datasheet(28/47 Pages) AMSCO

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AS3910

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.11.3 Interrupt Register and Associated Registers

Note:

Default setting is set at power up and after Set Default command.

Note:

At power up and after Set Default command, content of this register is set to 0.

After Interrupt register read, its content is set to 0

Table 17. Mask Interrupt Register

Address # 07: Mask Interrupt Register

type: RW

Bit

Name

Def.

Function

Comments

M_osc

mask INTR when oscillator frequency is stable

6M_nfc

mask INTR due to nfc event

5M_wl

mask INTR due to FIFO water level

4M_rxs

mask INTR due to end of receive

3M_txe

mask INTR due to end of transmission

2M_err

mask INTR due to error in receive data coding

1M_crc

mask INTR due to CRC error

0M_col

mask INTR due to bit collision

Table 18. Interrupt Register

Address # 08: Interrupt Register

type: R

Bit

Name

Function

Comments

I_osc

INTR when oscillator frequency is stable

Set after enable

6I_nfc

INTR due to nfc event

Set when nfc_t is 1 and en=0 informing that an RF field has

been detected,

Set when transmission could not be done due to detection of

RF field during RF Collision Avoidance

5I_wl

INTR due to FIFO water level

Set during receive, informing that FIFO is almost full and has

to be read out.

Set during transmit, informing that FIFO is almost empty and

that additional data has to be sent.

4I_rxs

INTR due to end of receive

3I_txe

INTR due to end of transmission

2I_err

INTR due to error in receive data coding

This includes parity error and framing error

1I_crc

INTR due to CRC error

0I_col

INTR due to bit collision

Valid only for ISO-14443A

Table 19. FIFO Status Register

Address # 09: FIFO Status Register

type: R

Bit

Name

Function

Comments

fifo_b5

Number of bytes (binary coded) in the FIFO which

were not read out

Valid range is from 000000 to 100000

fifo_b4

fifo_b3

fifo_b2

fifo_b1

fifo_b0

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