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Transcend Information Inc.

Ver 1.3

21

Host Pausing an Ultra DMA Data-In Burst

The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in

below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12:

Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing

Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data

burst has been transferred.

(b) The host shall pause an Ultra DMA data burst by negating -HDMARDY.

(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two

additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host

shall be prepared to receive zero, one, two or three additional data words. The additional data words

(e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY.

ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.

NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.

Notes:

-HDMARDY is negated.

(2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device.

(3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode.