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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM1808AZCE4 데이터시트(PDF) 76 Page - Texas Instruments |
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AM1808AZCE4 데이터시트(HTML) 76 Page - Texas Instruments |
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76 / 264 page  0.1 µF 0.01 µF 50R 1.14V-1.32V 50R VSS PLLn_VDDA PLLn_VSSA FerriteBead:MurataBLM31PG500SN1L orEquivalent AM1808 SPRS653 – FEBRUARY 2010 www.ti.com 6.6.1 PLL Device-Specific Information The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8. Figure 6-8. PLL External Filtering Components The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology. The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1. 76 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
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