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AM1808AZCE4 데이터시트(PDF) 117 Page - Texas Instruments

부품명 AM1808AZCE4
상세설명  AM1808 ARM Microprocessor
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AM1808AZCE4 데이터시트(HTML) 117 Page - Texas Instruments

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SPRS653 – FEBRUARY 2010
6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 6-21. CK and ADDR_CTRL Routing and Topology
Table 6-34. CK and ADDR_CTRL Routing Specification
No.
Parameter
Min
Typ
Max
Unit
Notes
1
Center to Center CK-CKN Spacing
2w
See Note (1)
2
CK A to B/A to C Skew Length Mismatch
25
Mils
See Note (2)
3
CK B to C Skew Length Mismatch
25
Mils
4
Center to center CK to other DDR2/mDDR trace spacing
4w
See Note (1)
5
CK/ADDR_CTRL nominal trace length
CACLM-50
CACLM
CACLM+50
Mils
See Note (3)
6
ADDR_CTRL to CK Skew Length Mismatch
100
Mils
7
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
100
Mils
8
Center to center ADDR_CTRL to other DDR2/mDDR trace spacing
4w
See Note (1)
9
Center to center ADDR_CTRL to other ADDR_CTRL trace spacing
3w
See Note (1)
10
ADDR_CTRL A to B/A to C Skew Length Mismatch
100
Mils
See Note (2)
11
ADDR_CTRL B to C Skew Length Mismatch
100
Mils
(1)
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2)
Series terminator, if used, should be located closest to device.
(3)
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
117
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Product Folder Link(s): AM1808



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