PixArt Imaging Inc.

PAC107

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PixArt Imaging Inc.

V1.4, Aug, 2005

reload/capture registers (RCAP2H, RCAP2L) into the timer registers (TH2, TL2). The

values in RCAP2H and RCAP2L are preset by software.

If EXEN2 = 1, the timer registers are reloaded by either a timer overflow or a high-to-low

transition at external input T2EX. This transition also sets the EXF2 bit in the T2CON

register. Either TF2 or EXF2 bit can generate a timer 2 interrupt request. TR2 must be

enabled when

running this mode.

Up/Down Counter Operation

When DCEN = 1, timer 2 operates as an up/down counter. External pin T2EX controls the

direction of the count. When T2EX is high, timer 2 counts up. The timer overflow occurs at

FFFFH which sets the timer 2 overflow flag (TF2) and generates an interrupt request. The

overflow also causes the 16-bit value in RCAP2H and RCAP2L to be loaded into the timer

registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the

timer registers (TH2, TL2) equals the value stored in RCAP2H and RCAP2L. The

underflow sets the TF2 bit and reloads FFFFH into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the

count. When timer 2 operates as an up/down counter, EXF2 does not generate an interrupt.

This bit can be used to provide 17-bit resolution. TR2 must be enabled when running this

mode.