PAC407BCA/PAC407BCW

CMOS Image Sensor IC

Version 1.7, 13 Sep

2004

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

13

During read cycle, the master generates start condition and then place the 1st byte data that combine slave

address (7 bits) with a read/write control bit to SDA line. After slave issue acknowledgment, 8 bits DATA

was placed on SDA line by PAC407. The 8 bit data was read from PAC407 internal control register that

address was assigned by previous write cycle. Following the master acknowledgment, the PAC407 place

the next 8 bits data (address is increased automatically) on SDA line and then transfer to master serially.

The DATA and Am cycles are repeated until the last byte read. After last byte read, Am is no longer

generated by master but instead of keeping SDA line as high. The slave (PAC407) must releases SDA line

back to master to generate STOP condition. (Please refer to Figure 5.3.)

Figure 5.3 Data Transfer Format

5.3.

2TM

IC

Bus Timing

IC

Bus Timing

5.4.

2TM

IC

Bus Timing Specification

STANDARD-MODE

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

SCL clock frequency

10

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated.

4.0

-

µs

Low period of the SCL clock

4.7

-

µs

HIGH period of the SCL clock

0.75

-

µs

Set-up time for a repeated START condition

4.7

-

µs

IC

bus device

0

3.45

µs

Data set-up time

250

-

ns

Rise time of both SDA and SCL signals

30

N.D. (note)

ns

Fall time of both SDA and SCL signals

30

N.D. (note)

ns

Set-up time for STOP condition

4.0

-

µs

Bus free time between a STOP and START

4.7

-

µs

SDA

SCL

PS

S

SDA

SCL

S

Start

Condition

1-7

8

9

1-7

8

9

1-7

8

9

P

Stop

Condition

ACK

from

Receiver

Data

ACK

from

Receiver

Data

ACK

from

Receiver

R/W

Address