VT98521

2002-02-25

Page 4

MDST-0017-02

www.vaishali.com

Vaishali Semiconductor

747 Camden Avenue, Suite C

Campbell

CA 95008

Ph. 408.377.6060

Fax 408.377.6063

AC Characteristics

Table 6 AC Characteristics

VDD = 3V to 3.6V over the operating temperature range

Symbol

Parameter

Condition

Min

Typ

Max

Units

Input Crystal Frequency

5

27

MHz

Input clock frequency

5

50

MHz

Output Frequency,

24

220

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

up to 160 MHz

45

49 to 51

55

%

Output Clock Duty Cycle

1.5 V

160 MHz to 220 MHz

40

60

%

PLL Bandwidth

10

kHz

Output Enable Time, OE high to output on

50

ns

Output Disable time, OE low to Tri-state

50

ns

Absolute Clock period Jitter

Deviation from mean

70

ps

One Sigma Clock Period Jitter

25

ps

Note1: External Crystal Connection

.

The external crystal should be connected in as close physical proximity to the VT98521 as possible. The crystal should be a

fundamental mode, parallel resonant. Do not use third overtone. External load capacitors should be fitted in accordance with the

crystal manufacturer’s specifications.

Note2: Decoupling and termination

.

Decoupling capacitors of 0.01

µF and 0.1 µF should be connected between VDD and Ground. Capacitors should be mounted as

close to the chip as possible. A 33Ω termination resistor may be connected in series with the clock output in order to minimize ringing

and reflections.

Figure 3. External Crystal Connection Block Diagram

Crystal

CLK3

106.25MHz

X2

X1

33pF

XTAL OSC

PLL

CLOCK

GEN.

OE

External Crystal

Load Capacitors

CLK

X2

X1

XTAL OSC

PLL

OE

External Crystal

Load Capacitors