ADS5400IPZPR datasheet(13/48 Pages) TI

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CLKINP

RESETP

tPD-CLKDIV4

tRSU

tRH

CLKOUTAP

DATA BUSB

SYNCOUTB

(OVRBpins)

DATA BUS A

N+1

N+2

CLKOUTA isresetafter 7.5 CLKINcycles (+ tPD-CLKDIV4 )

SampleNandRESET

pulsecapturedhere

N+1

sampled

Phase 0: CLKOUT indesired

stateafterpowerup

Phase 1: misalignedby 1

clockafterpowerup

Phase 2: misalignedby 2

clocksafterpowerup

Phase 3: misalignedby 3

clocksafterpowerup

CLKOUTBP

Phase 0: CLKOUT indesired

stateafterpowerup

Phase 1: misalignedby 1

clockafterpowerup

Phase 2: misalignedby 2

clocksafterpowerup

Phase 3: misalignedby 3

clocksafterpowerup

LatencyofN+1 is 7.5 CLKINcycles

tPD-ADATA

IfSYNCmodeisenabled,

theOVRBpinsbecomeSYNCOUTBpins

LatencyofNandSYNCOUTBarematchedto 7.5 CLKINcycles

ThephaseofdatashownpriortoresetmatchesCLKOUTBinphase 0

ThephaseofdatashownpriortoresetmatchesCLKOUTA inphase 0

tPD-CLKDIV4

Sync

CLKOUTBisresetafter 6.5 CLKINcycles (+ tPD-CLKDIV4 )

output

N+1

output

tsu

PD-BDATA

ADS5400

www.ti.com

SLAS611B – OCT 2009 – REVISED MARCH 2010

Timing Diagrams (continued)

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase

will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT

phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of

repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the

CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that

is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a

SYNCOUT pulse, which behaves as a data bit.

Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4

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