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ADCLK944BCPZ-R7 데이터시트(PDF) 11 Page - Analog Devices |
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ADCLK944BCPZ-R7 데이터시트(HTML) 11 Page - Analog Devices |
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11 / 12 page ![]() ADCLK944 Rev. 0 | Page 11 of 12 INPUT TERMINATION OPTIONS VREF VCC VT CLK CLK VREF VT CONNECT VT TO VCC. 50 Ω 50 Ω Figure 18. Interfacing to CML Inputs VREF VT CONNECT VT TO VCC − 2V. VCC – 2V 50 Ω 50 Ω CLK CLK Figure 19. Interfacing to PECL Inputs CONNECT VT TO VREF. 50 Ω 50 Ω CLK CLK VREF VT Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS CONNECT VT, VREF, AND CLK TOGETHER. PLACE A BYPASS CAPACITOR FROM VT TO GROUND. ALTERNATIVELY, VT, VREF, AND CLK CAN BE CONNECTED TOGETHER, GIVING A CLEANE LAY 50 Ω 50 Ω CLK CLK R OUT AND A 180° PHASE SHIFT. Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs |
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