WM2617

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 October 2000

8

SERIAL

INTERFACE

REGISTER

D12 = LOW

D15 = LOW

DOUBLE

BUFFER LATCH

LATCH B

TO DAC B

LATCH A

TO DAC A

Figure 8 Latch B and Double Buffer Write

DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH)

The SIR data are written to the double buffer only. Latch A and B contents are unaffected.

SERIAL

INTERFACE

REGISTER

D12 = HIGH

D15 = LOW

DOUBLE

BUFFER

LATCH B

TO DAC B

LATCH A

TO DAC A

Figure 9 Double Buffer Only Write

OPERATIONAL EXAMPLES

1. changing the latch A data from zero to full code

Assuming that latch A starts at zero code (e.g., after power up), the latch can be filled with 1s by

writing (bit D15 on the left, D0 on the right)

1X0X 1111 1111 11xx

to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The

other X can be zero or one (don’t care).

The latch B contents and DAC B output are not changed by this write unless the double buffer

contents are different from the latch B contents. This can only be true if the last write was a

double buffer-only write.

2. changing the latch B data from zero to full code

Assuming that latch B starts at zero code (e.g., after power up), the latch can be filled with 1s by

writing (bit D15 on the left, D0 on the right).

0X00 1111 1111 11xx

to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The

data (bits D0 to D11) are written to both the double buffer and latch B.

The latch A contents and the DAC A output are not changed by this write.

3. double buffered change of both DAC outputs

Assuming that DACs A and B start at zero code (e.g., after power up), if DAC A is to be driven to

mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this

can be achieved as follows: