NX2142ACUTR datasheet(18/18 Pages) MICROSEMI

18 / 18 page

NX2142/2142A

Rev. 1.1

10/28/07

4. Drain of the low-side MOSFET and source of

the high-side MOSFET need to be connected thru a

plane ans as close as possible. A snubber nedds to be

placed as close to this junction as possible.

5. Source of the lower MOSFET needs to be con-

nected to the GND plane with multiple vias. One is not

enough. This is very important. The same applies to

the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to

MOSFET gate as possible. The gate traces should be

wide and short. A place for gate drv resistors is needed

to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by-

passing capacitor needs to be placed first around the

IC and as close as possible. The capacitor on comp to

GND or comp back to FB needs to be place as close to

the pin as well as resistor divider.

8. The output sense line which is sensing output

back to the resistor divider should not go through high

frequency signals.

9. All GNDs need to go directly thru via to GND

plane.

10. The feedback part of the system should be

kept away from the inductor and other noise sources,

and be placed close to the IC.

11. In multilayer PCB, separate power ground and

analog ground. These two grounds must be connected

together on the PC board layout at a single point. The

goal is to localize the high current path to a separate

loop that does not interfere with the more sensitive ana-

log control function.

to reduce the EMI radiated by the power loop due to

the high switching currents through them.

2. Low ESR capacitor which can handle input

RMS ripple current and a high frequency decoupling

ceramic cap which usually is 1uF

need to be practi-

cally touching the drain pin of the upper MOSFET, a

plane connection is a must.

3. The output capacitors should be placed as close

as to the load as possible and plane connection is re-

quired.

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