WM2638

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 99

7

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference

input voltage and the input code according to the following relationship:

Output voltage =

( )

4096

CODE

V

2

REF

INPUT

OUTPUT

1111

1111

1111

( )

4096

4095

V

2

REF

:

:

1000

0000

0001

( )

4096

2049

V

2

REF

1000

0000

0000

( )

REF

REF

V

4096

2048

V

2

=

0111

1111

1111

( )

4096

2047

V

2

REF

:

:

0000

0000

0001

( )

4096

1

V

2

REF

0000

0000

0000

0V

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a

2k

Ω load with a 100pF load capacitance.

SERIAL INTERFACE

When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data

clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input

register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers

the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register

(see Table 2).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

MHz

20

t

t

1

min

WCL

min

WCH

=

+

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC

settling time to 12 bits limits the update rate for large input step transitions.