WM8192

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WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

22

REGISTER

BIT

NO

BIT

NAME(S)

DEFAULT

DESCRIPTION

0

VSMPDET

0

0 = Normal operation, signal on VSMP input pin is applied directly to

Timing Control block.

1 = Programmable VSMP detect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP input pin

and is applied to Timing Control block.

3:1

VDEL[2:0]

000

When VSMPDET = 0 these bits have no effect.

When VSMPDET = 1 these bits set a programmable delay from the

detected edge of the signal applied to the VSMP pin. The internally

generated pulse is delayed by VDEL MCLK periods from the detected

edge.

See Figure 13, Internal VSMP Pulses Generated for details.

Setup

Register 5

4

POSNNEG

0

When VSMPDET = 0 this bit has no effect.

When VSMPDET = 1 this bit controls whether positive or negative edges

are detected:

0 = Negative edge on VSMP pin is detected and used to generate internal

timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate internal

timing pulse.

See Figure 13 for further details.

Setup

Register 6

3:0

SELDIS[3:0]

0000

Selective power disable register - activated when SELPD = 1.

Each bit disables respective cell when 1, enabled when 0.

SELDIS[0] = Red CDS, PGA

SELDIS[1] = Green CDS, PGA

SELDIS[2] = Blue CDS, PGA

SELDIS[3] = ADC

Offset DAC

(Red)

7:0

DAC[7:0]

0

Red channel offset DAC value.

Offset DAC

(Green)

7:0

DAC[7:0]

0

Red channel offset DAC value

Offset DAC

(Blue)

7:0

DAC[7:0]

0

Red channel offset DAC value

Offset DAC

(RGB)

7:0

DAC[7:0]

0

A write to this register location causes the red, green and blue offset DAC

registers to be overwritten by the new value

PGA gain

(Red)

7:0

PGA[7:0]

0

Determines the gain of the red channel PGA according to the equation:

Red channel PGA gain = 208/(283-PGA[7:0])

PGA gain

(Green)

7:0

PGA[7:0]

0

Determines the gain of the green channel PGA according to the equation:

Green channel PGA gain = 208/(283-PGA[7:0])

PGA gain

(Blue)

7:0

PGA[7:0]

0

Determines the gain of the blue channel PGA according to the equation:

Blue channel PGA gain = 208/(283-PGA[7:0])

PGA gain

(RGB)

7:0

PGA[7:0]

0

A write to this register location causes the red, green and blue PGA gain

registers to be overwritten by the new value

Table 6 Register Control Bits