Advanced Information

WM9707

WOLFSON MICROELECTRONICS LTD

AI Rev 2.2 January 2001

25

DATA BIT

FUNCTION

READ/WRITE

WM9707 SUPPORT

VRA

Enables variable rate audio mode

Read/write

Yes

DRA

Enable double rate audio mode

Read/write

No

VRM

Enables variable rate Mic ADC

Read/write

No

CDAC

Indicates centre DAC ready

Read

No

SDAC

Indicates surround DAC ready

Read

No

LDAC

Indicates LFE DAC ready

Read

No

MADC

Indicates Mic ADC ready

Read

No

PRI

Set to turn off centre DAC

Read/write

No

PRJ

Set to turn off surround DACs

Read/write

No

PRK

Set to turn off LFE DACs

Read/write

No

PRL

Set to turn off Mic ADC

Read/write

No

Table 14 Extended Audio Status and Control Register

REGISTER 2Ch TO 32h – AUDIO SAMPLE RATE CONTROL REGISTERS

These registers are read/write registers that are written to, to select alternative sample rates for the

audio PCM converters. Default is the 48ks/s rate. Note that only Revision 2.1 recommended rates

are supported by the WM9707, selection of any other unsupported rates will cause the rate to default

to the nearest supported rate, and the supported rate value to be latched and so read back.

Note that the SPDIF mode only supports 48ks/s rate.

REGISTERS 36h AND 38h – 6 CHANNEL VOLUME CONTROL

These read/write registers control the output volume of the optional four PCM channels. (not

supported by the WM9707)

VENDOR RESERVED REGISTERS (INDEX 5Ah - 7Ah)

These registers are vendor specific. Do not write to these registers unless the Vendor ID register has

been checked first to ensure that the driver knows the source of the AC ‘97 component.

SPDIF DIGITAL AUDIO DATA OUTPUT – (INDEX 5Ch)

The WM9707 provides an SPDIF output. In order to enable this output, bit SPDF in Register 5Ch

should be set. Additionally, a bit SCMS in Register 5Ch may also be set, which sets the copyright

flag in the IEC958 data, allowing serial copy protect mechanisms to be removed.

The WM9707 can be programmed to automute the DACs. By setting the mute bit, the WM9707 will

mute the DACs when it detects a continuous sequence of 1024 zeros.