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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS43L22 데이터시트(PDF) 17 Page - Cirrus Logic |
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CS43L22 데이터시트(HTML) 17 Page - Cirrus Logic |
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17 / 66 page  DS792F2 17 CS43L22 Confidential Draft 3/4/10 SWITCHING SPECIFICATIONS - I²C CONTROL PORT Inputs: Logic 0 = DGND; Logic 1 = V; SDA CL =30pF. 13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Parameters Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 550 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 13) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc -1 µs Fall Time SCL and SDA tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL t irs RESET Figure 4. Control Port Timing - I²C |
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