X24042

11

SCL

SDA

8th BIT

WORD n

ACK

tWR

STOP

CONDITION

START

CONDITION

X24042

ADDRESS

WRITE CYCLE LIMITS

Symbol

Parameter

Min.

Max.

Units

Write Cycle Time

5

10

ms

3849 PGM T09

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

erase/program cycle. During the write cycle, the X24042

bus interface circuits are disabled, SDA is allowed to

remain high, and the device does not respond to its slave

address.

3849 FHD F05

device requires to perform the internal write operation.

Write Cycle Timing

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

SYMBOL TABLE

3849 FHD F17

120

100

80

40

60

20

20

40

60

80 100 120

0

0

BUS CAPACITANCE (pF)

MIN.

RESISTANCE

MAX.

RESISTANCE

RMAX =

CBUS

tRMAX

RMIN =

IOL MIN

VCC MAX

=1.8K

Ω

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

OUTPUTS

INPUTS

WAVEFORM