6

X24C01

Figure 6. ACK Polling Sequence

Acknowledge Polling

The disabling of the inputs can be used to take advan-

tage of the typical 5 ms write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation the X24C01 initiates the internal write cycle.

ACK polling can be initiated immediately. This involves

issuing the start condition followed by the word address

for a write operation. If the X24C01 is still busy with the

write operation no ACK will be returned. If the X24C01

has completed the write operation an ACK will be

returned and the controller can then proceed with the

next read or write operation.

READ OPERATIONS

Read operations are initiated in the same manner as

write operations with exception that the R/W bit of the

word address is set to a one. There are two basic read

operations: byte read and sequential read.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a stop condition.

Byte Read

To initiate a read operation, the master sends a start

condition followed by a seven bit word address and a

read bit. The X24C01 responds with an acknowledge

and then transmits the eight bits of data. The read

operation is terminated by the master; by not responding

with an acknowledge and by issuing a stop condition.

Refer to Figure 7 for the start, word address, read bit,

acknowledge and data transfer sequence.

WRITE OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE

START

ISSUE SLAVE

ADDRESS AND R/W = 0

ACK

RETURNED?

NEXT

OPERATION

A WRITE?

PROCEED

ISSUE STOP

NO

YES

YES

PROCEED

ISSUE STOP

NO

3837 FHD F11

Figure 7. Byte Read

3837 FHD F12

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24C01

S

T

A

R

T

WORD

ADDRESS n

S

T

O

P

P

A

C

K

DATA n

R

/

W

L

S

B

S

M

S

B