SS6802CGSTR datasheet(6/10 Pages) SSC

6 / 10 page

02/26/2008 Rev.1.00

www.SiliconStandard.com

BLOCK DIAGRAM

VCC

GND

VCC

450

OVERCURRENT

DELAY CIRCUIT

OVERCURRENT

DETECTOR

CHARGE

DETECTION

OVERDISCHARGE

DETECTOR 2

TIMING

GENERATION

OVERCHARGE

DETECTOR 1

OVERCHARGE

DELAY CIRCUIT

OVERDISCHARGE

DETECTOR 1

OVERDISCHARGE

DELAY CIRCUIT

OVERCHARGE

DETECTOR 2

LOGIC

CONTROL

WAKE-

POWER-

DOWN

UNBALANCE

DISCHARGE

PIN DESCRIPTIONS

PIN 1: OC

- PMOS

open

drain

output

for

control

the

charge

control

MOSFET M2. When overcharge

occurs, this pin sources current to

switch the external NPN Q1 on,

and

charging

inhibited

turning off the charge control

MOSFET M2.

PIN 2: OD

- Output pin for control of the

discharge control MOSFET M1.

When overdischarge occurs, this

pin goes low to turn off the

discharge control MOSFET M1

and discharging is inhibited.

PIN 3: TD

- Overdischarge delay time setting

pin.

PIN 4: GND - Ground pin. This pin is to be

connected

the

negative

terminal of the lower battery cell.

PIN 5: TC

- Overcharge delay time setting

pin.

PIN 6: VC

- To be connected to the positive

terminal of the lower cell and

the negative terminal of the

upper cell.

PIN 7: CS

- Input pin for current sensing.

Using the drain-source voltage

the

discharge

control

MOSFET M1 (voltage between

and

GND),

senses

discharge current during normal

mode

and

detects

whether

charging

current

present

during power down mode.

PIN 8: VCC - Power supply pin. It is to be

connected

the

positive

terminal of the upper cell.

SS6802

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