| 전자부품 데이터시트 검색엔진 |
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X76F128HE 데이터시트(PDF) 11 Page - Xicor Inc. |
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X76F128HE 데이터시트(HTML) 11 Page - Xicor Inc. |
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11 / 17 page ![]() X76F128 11 AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) Notes: 1. Typical values are for TA = 25˚C and VCC = 5.0V Notes: 2. Cb = Total Capacitance of one bus line in pf. Symbol Parameter Min Typ(1) Max Units fSCL SCL Clock Frequency, X76F128 0 400 KHz fSCL SCH Clock Frequency, X76F128–2.7 0 250 KHz tIN (1) Pulse width of spikes which must be suppressed by the input filter 50 100 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.3 0.9 µs tBUF Time the bus must be free before a new transmit can start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 300 ns tR SDA and SCL Rise Time 20 + 0.1 x Cb (2) 300 ns tF SDA and SCL Fall Time 20 + 0.1 x Cb (2) 300 ns tSU:CS CS Setup Time 200 ns tHD:CS CS Hold Time 100 ns fSCL_RST SCL Clock Frequency during Response to Reset 400 kHz tSR Device Select to RST active 200 ns tNOL RST to SCL Non-Overlap 500 ns tRST RST High Time 2.25 µs tSU:RST Response to Reset Setup Time 1.25 µs tLOW_RST Clock LOW during Response to Reset 1.25 µs tHIGH_RST Clock HIGH during Response to Reset 1.25 µs tRDV RST LOW to SDA Valid During Response to Reset 0 500 ns tCDV CLK LOW to SDA Valid During Response to Reset 0 500 ns tDHZ Device Deselect to SDA high impedance 0 500 ns 7052 FM T14 |
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