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ADRF6601ACPZ-R7 데이터시트(PDF) 16 Page - Analog Devices |
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ADRF6601ACPZ-R7 데이터시트(HTML) 16 Page - Analog Devices |
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16 / 24 page ![]() ADRF6601 Rev. 0 | Page 16 of 24 LO SELECTION LOGIC The downconverting mixer in the ADRF6601 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer. The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 9. Table 9. LO Selection Logic Pins1 Register 5 Bits1 Outputs Pin 16 (PLL_EN) Pin 36 (LODRV_EN) Bit DB6 (PLEN) Bit DB3 (LDRV) Output Buffer LO 0 X 0 X Disabled External 0 X 1 X Disabled External 1 X 0 X Disabled External 1 0 1 0 Disabled Internal 1 X 1 1 Enabled Internal 1 1 1 X Enabled Internal 1 X = don’t care. |
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