HAL855UT-K datasheet(24/42 Pages) MICRONAS

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HAL855

DATA SHEET

Nov. 26, 2008; DSH000149_003EN

Micronas

3.6.1. Specification of Biphase-M Output

In case of output format Biphase-M, a continuous data

stream is provided. It consists of:

– 1 SYNC bit defining the bit time tp0,

– 14 data bits (DAT)

– 1 parity bit (DP)

– a gap (signal quiescent) of 8 x tp0

The complete signal period is T = 24 x tp0.

The signal quiescent level and the polarity of the

SYNC bit is shown in Fig. 3–5.

Definition of Biphase-M Pulses

A logical “0” is coded as no output level change within

the bit time. A logical “1” is coded as an output level

change between 50% and 80% of the bit time. After

each bit, an output level change occurs.

Data Bits (DAT)

The 12 MSB of the 14 data bits (DAT) contain the digi-

tal output reading.

Data Parity Bit (DP)

This parity bit is “1” if the number of zeros within the 14

data bits is even. The parity bit is “0” if the number of

zeros is odd.

Note: If the part number output is activated the part

number will be

transmitted

2 times

after

power-up (see also (see Fig. 4–6 on page 31).

The first Biphase-M protocol respectively the

first PWM period after power-up is not valid.

Fig. 3–5: Output format Biphase-M: continuous data stream

Type

SYNC Bit Polarity

HAL855

negative

DAT

SYNC BIT

HAL855:

VOUT

8 x tp0

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