74HC73_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 19 March 2008

8 of 16

NXP Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

11. Waveforms

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

Fig 6.

Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J

and K to nCP set-up and hold times, the output transition times and the maximum clock frequency

nCP input

nJ, nK

input

001aab983

nQ output

GND

90 %

10 %

10 %

10 %

10 %

90 %

90 %

90 %

GND

nQ output

Measurement points are given in Table 8.

Fig 7.

Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width

and the nR to nCP removal time

001aab984

nQ output

GND

GND

nR input

nQ output

nCP input