74LVC2G38GD datasheet(8/16 Pages) NXP

8 / 16 page

74LVC2G38_7

Product data sheet

Rev. 07 — 20 March 2009

8 of 16

NXP Semiconductors

74LVC2G38

Dual 2-input NAND gate; open drain

Table 9.

Measurement points

Supply voltage

Input

Output

VCC

1.65 V to 1.95 V

0.5

× V

VOL + 0.15 V

0.5

× V

2.3 V to 2.7 V

0.5

× V

VOL + 0.15 V

0.5

× V

2.7 V

1.5 V

VOL + 0.3 V

1.5 V

3.0 V to 3.6 V

1.5 V

VOL + 0.3 V

1.5 V

4.5 V to 5.5 V

0.5

× VCC

VOL + 0.3 V

0.5

× V

Test data is given in Table 10

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 9.

Test circuit for measuring switching times

VEXT

VCC

001aae235

DUT

PULSE

GENERATOR

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

Table 10.

Test data

Supply voltage

Input

Load

VEXT

VCC

tr, tf

tPLZ, tPZL

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

× VCC

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

× V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

6 V

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

6 V

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500

Ω

× V

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