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EP7311 데이터시트(PDF) 21 Page - Cirrus Logic |
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EP7311 데이터시트(HTML) 21 Page - Cirrus Logic |
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21 / 58 page ![]() DS506F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 21 EP7311 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes. Parameter Symbol Min Typ Max Unit EXPCLK rising edge to nCS assert delay time tCSd 2 8 20 ns EXPCLK falling edge to nCS deassert hold time tCSh 2 7 20 ns EXPCLK rising edge to A assert delay time tAd 4 9 16 ns EXPCLK falling edge to A deassert hold time tAh 310 19 ns EXPCLK rising edge to nMWE assert delay time tMWd 3 6 10 ns EXPCLK rising edge to nMWE deassert hold time tMWh 3 6 10 ns EXPCLK falling edge to nMOE assert delay time tMOEd 3 7 10 ns EXPCLK falling edge to nMOE deassert hold time tMOEh 2 7 10 ns EXPCLK falling edge to HALFWORD deassert delay time tHWd 2 8 20 ns EXPCLK falling edge to WORD assert delay time tWDd 2 8 16 ns EXPCLK rising edge to data valid delay time tDv 813 21 ns EXPCLK falling edge to data invalid delay time tDnv 615 30 ns Data setup to EXPCLK falling edge time tDs -- 1 ns EXPCLK falling edge to data hold time tDh -- 3 ns EXPCLK rising edge to WRITE assert delay time tWRd 511 23 ns EXPREADY setup to EXPCLK falling edge time tEXs -- 0 ns EXPCLK falling edge to EXPREADY hold time tEXh -- 0 ns |
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