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CS5461 데이터시트(PDF) 39 Page - Cirrus Logic |
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CS5461 데이터시트(HTML) 39 Page - Cirrus Logic |
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39 / 45 page ![]() CS5461 DS546F2 39 7.16 VSAGDuration: Voltage Sag-Detect Duration Level Address: 24 Default** = 0x000000 This Register sets the number of conversions over to accumulate RMS voltage for comparison against the VSA- GLEVEL. Setting this register to zero will disable the VSAG feature. 7.17 Control Register Register Address: 28 Default** = 0x000000 FAC 1 = enable anti-creep for FOUT pulse output function. EAC 1 = enable anti-creep for EOUT pulse output function. STOP 1 = used to terminate the new EEBOOT sequence. MECH 1 = widens EOUT and EDIR pulses for mechanical counters. INTOD 1 = Converts INT output to open drain configuration. NOCPU 1 = saves power by disabling the CPUCLK external drive pin. NOOSC 1 = saves power by disabling the crystal oscillator circuit. STEP 1 = enables stepper-motor signals on the EOUT/EDIR pins. MSB LSB 223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FAC EAC STOP 7 654 32 10 MECH INTOD NOCPU NOOSC STEP |
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