10F222 datasheet(48/86 Pages) MICROCHIP

48 / 86 page

PIC10F220/222

DS41270E-page 46

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] BTFSS f,b

Operands:

≤ f ≤ 31

≤ b < 7

Operation:

skip if (f<b>) = 1

Status Affected:

None

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed instead,

making this a two-cycle instruction.

CALL

Subroutine Call

Syntax:

[ label ] CALL k

Operands:

≤ k ≤ 255

Operation:

(PC) + 1

→ Top of Stack;

→ PC<7:0>;

(Status<6:5>)

→ PC<10:9>;

→ PC<8>

Status Affected:

None

Description:

Subroutine call. First, return

address (PC + 1) is pushed onto

the stack. The eight-bit immediate

address is loaded into PC bits

<7:0>. The upper bits PC<10:9>

are loaded from STATUS<6:5>,

PC<8> is cleared. CALL is a two-

cycle instruction.

CLRF

Clear f

Syntax:

[ label ] CLRF

Operands:

≤ f ≤ 31

Operation:

00h

→ (f);

→ Z

Status Affected:

Description:

The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

None

Operation:

00h

→ (W);

→ Z

Status Affected:

Description:

The W register is cleared. Zero bit

(Z) is set.

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRWDT k

Operands:

None

Operation:

00h

→ WDT;

→ WDT prescaler (if assigned);

→ TO;

→ PD

Status Affected:

TO, PD

Description:

The CLRWDT instruction resets the

WDT. It also resets the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

COMF

Complement f

Syntax:

[ label ] COMF

f,d

Operands:

≤ f ≤ 31

∈ [0,1]

Operation:

(f)

→ (dest)

Status Affected:

Description:

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back in

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