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LPC1759 데이터시트(PDF) 49 Page - NXP Semiconductors |
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LPC1759 데이터시트(HTML) 49 Page - NXP Semiconductors |
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49 / 64 page ![]() LPC1759_58_56_54_52_51_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 26 January 2010 49 of 64 NXP Semiconductors LPC1759/58/56/54/52/51 32-bit ARM Cortex-M3 microcontroller 11.7 SSP interface [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. Table 13. Dynamic characteristic: SSP interface Tamb = 25 °C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tsu(SPI_MISO) SPI_MISO set-up time measured in SPI Master mode; see Figure 15 [1] 30 - - ns Fig 15. SSP MISO line set-up time in SPI Master mode tsu(SPI_MISO) SCK shifting edges MOSI MISO 002aad326 sampling edges |
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