Application information

L6564

20/34

Doc ID 16202 Rev 1

6

Application information

6.1

Overvoltage protection

Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator

close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A

pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a

separate resistor divider (R3 high, R4 low, see Figure 34). This divider is selected so that

the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually

larger than the maximum Vo that can be expected.

51 k

Ω.

When this function is triggered, the gate drive activity is immediately stopped until the

voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be

selected without any constraints. The unique criterion is that both dividers have to sink a

current from the output bus which needs to be significantly higher than the bias current of

both INV and PFC_OK pins.

Figure 34.

Output voltage setting, OVP and FFP functions: internal block diagram