M23LR64-R-DW6TSLASH2 datasheet(30/126 Pages) STMICROELECTRONICS

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I2C device operation

M24LR64-R

30/126

Doc ID 15170 Rev 9

5.5

Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 2 (on Serial Data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable

“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is

1010b.

Up to four memory devices can be connected on a single I2C bus. Each one is given a

unique 2-bit code on the Chip Enable (E0, E1) inputs. When the device select code is

received, the device only responds if the Chip Enable Address is the same as the value on

the Chip Enable (E0, E1) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Figure 10.

Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)

Table 15.

Operating modes

Mode

RW bit

Bytes

Initial sequence

Current Address Read

Start, device select, RW = 1

Random Address Read

Start, device select, RW = 0, Address

reStart, device select, RW = 1

Sequential Read

 1

Similar to Current or Random Address Read

Byte Write

Start, device select, RW = 0

Page Write

 4 bytes

Start, device select, RW = 0

Byte Write

Dev select

Byte address

Data in

Page Write

Dev select

Byte address

Data in 1

Data in 2

AI15115

Page Write

(cont'd)

Data in N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

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