P89LPC913FDH datasheet(13/66 Pages) NXP

13 / 66 page

P89LPC912_913_914_5

Product data sheet

Rev. 05 — 28 September 2007

13 of 66

NXP Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

P2.2, P2.3,

P2.5

I/O

Port 2: Port 2 is a 3-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the port

conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

P2.2/MOSI

I/O

P2.2 — Port 2 bit 2.

I/O

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,

when conﬁgured as slave, this pin is input.

P2.3/MISO

I/O

P2.3 — Port 2 bit 3.

I/O

MISO — SPI master in slave out. When conﬁgured as master, this pin is input,

when conﬁgured as slave, this pin is output.

P2.5/SPICLK

I/O

P2.5 — Port 2 bit 5.

I/O

SPICLK — SPI clock. When conﬁgured as master, this pin is output, when

conﬁgured as slave, this pin is input.

P3.0 to P3.1

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 3 pins as inputs and outputs depends upon the port

conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0/XTAL2/

CLKOUT

I/O

P3.0 — Port 3 bit 0.

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the ﬂash conﬁguration).

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source

for the Real-Time clock/system timer.

P3.1/XTAL1

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator or

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the Real-Time clock/system timer.

VSS

Ground: 0 V reference.

VDD

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

Table 5.

P89LPC913 pin description …continued

Symbol

Type

Description

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