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STM8S105C4B3TR 데이터시트(PDF) 83 Page - STMicroelectronics |
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STM8S105C4B3TR 데이터시트(HTML) 83 Page - STMicroelectronics |
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83 / 127 page ![]() Unit Max Typ Min Conditions Parameter Symbol V VDD + 0.3 V 0.7 x VDD Input high level voltage VIH mV 700 Hysteresis (1) Vhys kΩ 60 45 30 VDD = 5 V, VIN = VSS Pull-up resistor Rpu ns 20 (2) Fast I/Os load = 50 pF Rise and fall time(10 % - 90 %) tR, tF ns 125 (2) Standard and high sink I/OsLoad = 50 pF µA ±1 (2) VSS ≤ VIN ≤ VDD Input leakage current, analog and digital Ilkg nA ±250 (2) VSS ≤ VIN ≤ VDD Analog input leakage current Ilkg ana µA ±1 (2) Injection current ±4 mA Leakage current in adjacent I/O (2) Ilkg(inj) (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterization results, not tested in production. Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures 83/127 DocID14771 Rev 9 Electrical characteristics STM8S105xx |
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