PCA9541APWSLASH01 datasheet(19/41 Pages) NXP

19 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

19 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 9).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the

STOP condition (P) (see Figure 10).

Fig 9.

Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 10. Deﬁnition of START and STOP conditions

mba608

SDA

SCL

STOP condition

START condition

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