PCF8564AUSLASH5GBSLASH1 datasheet(23/44 Pages) NXP

23 / 44 page

PCF8564A_1

Product data sheet

Rev. 1 — 8 October 2009

23 of 44

NXP Semiconductors

PCF8564A

Real time clock and calendar

10. I2C-bus protocol

10.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the start procedure.

The PCF8564A acts as a slave receiver or slave transmitter. Therefore, the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

Two slave addresses are reserved for the PCF8564A:

Read: A3h (1010 0011)

Write: A2h (1010 0010)

The PCF8564A slave address is shown in Figure 15.

10.2 Clock and calendar READ or WRITE cycles

Figure 17, Figure 18, and Figure 19 show the I2C-bus conﬁguration for the different

PCF8564A READ and WRITE cycles. The word address is a 4-bit value that deﬁnes

which register is to be accessed next. The upper four bits of the word address are not

used.

Fig 16. Slave address

mce189

R/W

group 1

group 2

Fig 17. Master transmits to slave receiver (WRITE mode)

SLAVE ADDRESS

WORD ADDRESS

DATA

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

R/W

auto increment

memory word address

mbd822

n bytes

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