SC16C751B_2

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 02 — 10 October 2008

14 of 32

NXP Semiconductors

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger

levels.

7.3.1 FIFO mode

Table 8.

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7]

(MSB),

FCR[6] (LSB)

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO equals

the programmed trigger level. However, the FIFO will continue to be loaded

until it is full. Refer to Table 9.

5

FCR[5]

64-byte FIFO enable.

logic 0 = 16-byte mode (normal default condition)

logic 1 = 64-byte mode

4:3

FCR[4:3]

reserved

2

FCR[2]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

1

FCR[1]

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

0

FCR[0]

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Table 9.

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

16-byte operation

64-byte operation

001

1

014

16

108

32

1114

56