TUSB1310

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SLLSE16B – DECEMBER 2009 – REVISED JUNE 2010

Table 2-11. Power/Ground Signal Descriptions (continued)

SIGNAL NAME

TYPE

BALL NO.

DESCRIPTION

F6

F7

F8

F9

G6

G7

G8

G9

VSS

G

J6

J7

Digital ground

H6

H7

H8

H9

J8

J9

B11

F12

3

FUNCTIONAL DESCRIPTION

3.1

Power On and Reset

The TUSB1310 has two hardware reset pins, a chip reset RESETN and a logic reset PHY_RESETN. The

RESETN is used only at Power On. The PHY_RESETN can be used as a functional reset. The ULPI

register also has a software reset.

Until all power sources are supplied, the OUT_ENABLE pin can control the output driver enable. After all

power sources are supplied, the chip reset RESETN and a ULPI soft reset will be asserted by the link

layer. The power up sequence is described in section 3.1.4.

3.1.1

RESETN and PHY_RESETN – Hardware Reset

The RESETN sets all internal states to initial values. The link layer needs to hold the PHY in reset via the

RESETN until all power sources and the reference clock to the TUSB1310 are stable. All pins used for

strapping options must be set before RESETN de-assertion. All strapping option pins have internal pull-up

or pull-down to set default values, but if any non-default values are desired, they need to be controlled

externally by the link layer controller.

Table 3-1. Pin States in Chip Reset

PIPE CONTROL

STATE

VALUE

PIN NAME

TX_DETRX_LPBK

Inactive

0

TX_ELECIDLE

Active

1

TX_COMPLIANCE

Inactive

0

RX_POLARITY

Inactive

0

POWER_DOWN

U2

10b

TX_MARGIN2-0

Normal operating range

000b

TX_DEEMP

-3.5 dB

1

RATE

5.0 Gbps

1

TX_SWING

Full swing or half swing

0 or 1

RX_TERMINATION

Appropriate state

0 or 1

Copyright © 2009–2010, Texas Instruments Incorporated

FUNCTIONAL DESCRIPTION

17

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Product Folder Link(s): TUSB1310